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PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18
Integrated Device Technology, Inc.
IDT72511 IDT72521
FEATURES:
* Two side-by-side FIFO memory arrays for bidirectional data transfers * 512 x 18-Bit - 512 x 18-Bit (IDT72511) * 1024 x 18-Bit - 1024 x 18-Bit (IDT72521) * 18-bit data buses on Port A side and Port B side * Can be configured for 18-to-18-bit or 36-to-36-bit communication * Fast 35ns access time * Fully programmable standard microprocessor interface * Built-in bypass path for direct data transfer between two ports * Two fixed flags, Empty and Full, for both the A-to-B and the B-to-A FIFO * Two programmable flags, Almost-Empty and Almost-Full for each FIFO * Programmable flag offset can be set to any depth in the FIFO * Any of the eight flags can be assigned to four external flag pins * Flexible reread/rewrite capabilities * Six general-purpose programmable I/O pins * Standard DMA control pins for data exchange with peripherals * 68-pin PGA and PLCC packages
DESCRIPTION:
The IDT72511 and IDT72521 are highly integrated first-in, first-out memories that enhance processor-to-processor and processor-to-peripheral communications. IDT BiFIFOs integrate two side-by-side memory arrays for data transfers in two directions. The BiFIFOs have two ports, A and B, that both have standard microprocessor interfaces. All BiFIFO operations are controlled from the 18-bit wide Port A. Port B is also 18 bits wide and can be connected to another processor or a peripheral controller. The BiFIFOs have a 9-bit bypass path that allows the device connected to Port A to pass messages directly to the Port B device. Ten registers are accessible through Port A, a Command Register, a Status Register, and eight Configuration Registers. The IDT BiFIFO has programmable flags. Each FIFO memory array has four internal flags, Empty, Almost-Empty, Almost-Full and Full, for a total of eight internal flags. The Almost-Empty and Almost-Full flag offsets can be set to any depth through the Configuration Registers. These eight internal flags can be assigned to any of four external flag pins (FLGA-FLGD) through one Configuration Register. Port B has programmable I/O, reread/rewrite and DMA functions. Six programmable I/O pins are manipulated through
SIMPLIFIED BLOCK DIAGRAM
18-Bit FIFO
18-bits Data
Bypass
9-bits
18-bits Data
Port A
18-Bit FIFO
Port B
Programmable I/O Logic
I/O
Control
Processor Interface A Programmable Flag Logic
Registers
Processor Interface B Handshake Interface
Control
Flags
DMA
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The IDT logo is a registered trademark of Integrated Device Techology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
DECEMBER 1995
DSC-2668/6
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two Configuration Registers. The Reread and Rewrite controls will read or write Port B data blocks multiple times. The BiFIFO has three pins, REQ, ACK and CLK, to control DMA transfers from Port B devices.
PIN CONFIGURATIONS
11 10 09 08 07 06 05 04 03 02 01 A DB11 DB9 GND RB WB DB7 DB5 DB3 DB2 DB13 DB14 DB17 FLGB FLGD DB12 DB15 FLGA FLGC DB10 DB8 GND VCC DB16 DB6 DB4 DB13 CLK REQ RER R/WA PIO0 DB1 DB0 B ACK REW GND CSA C D E F PIO1 G DA0 DA1 H DA2 DA3 J G68-1
PGA TOP VIEW
A0
DA15 DA13 DA11
A1
DA17 DA14 DA12 DB13 PIO4 PIO5 DA9 PIO3 GND VCC GND PIO2 DA7 DB13 DA5 DA4 K L DA10 DA8
LDRER
DSA RS
LDREW
DA16 DA6
PIN 1
DESIGNATOR
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INDEX
D A5 D A6 D A7 D A16 PIO 2 LDREW GND RS V CC DS A GND LDRER PIO 3 D A8 D A9 D A10 PIO 4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
D A4 D A3 D A2 D A1 D A0 PIO 1 PIO 0 CS A R/W A GND RER REW REQ ACK CLK D B0 D B1
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
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52 51 50 49 48 47 46 45
PLCC TOP VIEW
44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D B2 D B3 D B4 D B5 D B6 D B7 D B16 W B (R/WB ) V CC R B (DS B) GND GND D B8 D B9 D B10 D B11 D B12
PIO 5 D A11 D A12 DA13 DA14 D A15 D A17 A0 A1 FLG D FLGC FLGB FLG A D B17 D B15 D B14 D B13
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PIN DESCRIPTION
Symbol DA0-DA17 Name Data A Chip Select A Data Strobe A Read/Write A I/O I/O I I I Description Data inputs and outputs for the 18-bit Port A bus. Port A is accessed when Chip Select A is LOW. Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is read out of Port A on the falling edge of Data Strobe when Chip Select is LOW. This pin controls the read or write direction of Port A. When CSA is LOW and R/WA is HIGH, data is read from Port A on the falling edge of DSA. When CSA is LOW and R/WA is LOW, data is written into Port A on the rising edge of DSA. When Chip Select A is asserted, A 0, A1, and Read/Write A are used to select one of six internal resources. Data inputs and outputs for the 18-bit Port B bus.
CSA DSA
R/WA
A0, A1 DB0-DB17
Addresses Data B Read B
I I/O
RB (DSB)
I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin functions as an output. This pin can function as part of an Intel-style interface (RB) or as part of a Motorola-style interface (DSB). As an Intel-style interface, data is read from Port B on a falling edge of RB. As a Motorola-style interface, data is read on the falling edge of DSB or written on the rising edge of DSB through Port B. The default is Intel-style processor mode. (RB as an input). I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin functions as an output. This pin can function as part of an Intel-style interface (WB) or as part of a Motorola-style interface (R/ WB). As an Intel-style interface, data is written to Port B on a rising edge of WB. As a Motorola-style interface, data is read (R/WB = HIGH) or written (R/WB = LOW) to Port B in conjunction with a Data Strobe B falling or rising edge. The default is Intel-style processor mode ( WB as an input.) I I I I I O Loads A B FIFO Read Pointer with the value of the Reread Pointer when LOW. Loads B A FIFO Write Pointer with the value of the Rewrite Pointer when LOW. Loads the Reread Pointer with the value of the AB FIFO Read Pointer when HIGH. Loads the Rewrite Pointer with the value of the BA FIFO Write Pointer when HIGH. When Port B is programmed in peripheral mode, asserting this pin begins a data transfer. Request can be programmed either active HIGH or active LOW. When Port B is programmed in peripheral mode, Acknowledge is asserted in response to a Request signal. This confirms that a data transfer may begin. Acknowledge can be programmed either active HIGH or active LOW. This pin is used to generate timing for ACK, peripheral mode.
WB (R/WB)
Write B
RER REW
LDRER LDREW REQ ACK
Reread Rewrite Load Reread Load Rewrite Request Acknowledge
CLK FLGAFLGD PIO0-PIO5
Clock Flags
I O
RB, WB, DSB
and R/WB when Port B is in the
These four outputs pins can be assigned any one of the eight internal flags in the BiFIFO. Each of the two internal FIFOs (AB and BA) has four internal flags: Empty, Almost-Empty, Almost-Full and Full. Six general purpose I/O pins. The input or output direction of each pin can be set independently.
Programmable Inputs/ Outputs Reset Power Ground
I/O
RS
VCC GND
I
A LOW on this pin will perform a reset of all BiFIFO functions. There are two +5V power pins. There are five Ground pins at 0V.
2668 tbl 01
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DETAILED BLOCK DIAGRAM
Reread Pointer CSA DSA R/WA A1 A0 Load Reread Port A Control Write Pointer Reread Port B Control LDRER LDREW RER REW RB (DSB) ==
Read Pointer
WB (R/WB) ==
A
18
B FIFO
18
Bypass Path
Port A DA0-DA17
9 9
Port B DB0-DB17
B
18
A FIFO
18
Read Pointer
Write Pointer Rewrite
Load Rewrite Rewrite Pointer Command Status Configuration 0 Programmable Flag Logic Configuration 1 Configuration 2 Configuration 3 Configuration 4 Configuration 5 Configuration 6 Configuration 7
16 FLGA* FLGB* FLGC* FLGD*
Reset
RS REQ* ACK* CLK
DMA Control
Programmable I/O Logic
PIO5 == PIO4 == PIO3 == PIO2 == PIO1 == PIO0 ==
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NOTES: (*) Can be programmed either active high or active low in internal configuration registerers. (==) Can be programmed through an internal configuration register to be either an input or an output.
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FUNCTIONAL DESCRIPTION
IDT's BiFIFO family is versatile for both multiprocessor and peripheral applications. Data can be sent through both FIFO memories concurrently, thus freeing both processors from laborious direct memory access (DMA) protocols and frequent interrupts. Two full 18-bit wide FIFOs are integrated into the IDT BiFIFO, making simultaneous data exchange possible. Each FIFO is monitored by separate internal read and write pointers, so communication is not only bidirectional, it is also totally independent in each direction. The processor connected to Port A of the BiFIFO can send or receive messages directly to the Port B device using the BiFIFO's 9-bit bypass path. The BiFIFO can be used in different bus configurations: 18 bits to 18 bits and 36 bits to 36 bits. One BiFIFO can be used for the 18- to 18-bit configuration, and two BiFIFOs are required for 36- to 36-bit configuration. This configuration can be extended to wider bus widths (54- to 54-bits, 72- to 72-bits, ...) by adding more BiFIFOs to the configuration. The microprocessor or microcontroller connected to Port A controls all operations of the BiFIFO. Thus, all Port A interface pins are inputs driven by the controlling processor. Port B can be programmed to interface either with a second processor or a peripheral device. When Port B is programmed in processor interface mode, the Port B interface pins are inputs driven by the second processor. If a peripheral device
is connected to the BiFIFO, Port B is programmed to peripheral interface mode and the interface pins are outputs. 18- to 18-bit Configurations A single BiFIFO can be configured to connect an 18-bit processor to another 18-bit processor or an 18-bit peripheral. The upper BiFIFO shown in each of the Figures 1 and 2 can be used in 18- to 18-bit configurations for processor and peripheral interface modes respectively. 36- to 36-bit Configurations In a 36- to 36-bit configuration, two BiFIFOs operate in parallel. Both BiFIFOs are programmed simultaneously, 18 data bits to each device. Figures 1 and 2 show multiple BiFIFOs configured for processor and peripheral interface modes respectively. Processor Interface Mode When a microprocessor or microcontroller is connected to Port B, all BiFIFOs in the configuration must be programmed to processor interface mode. In this mode, all Port B interface controls are inputs. Both REQ and CLK pins should be pulled LOW to ensure that the setup and hold time requirements for these pins are met during reset. Figure 1 shows the BiFIFO in processor interface mode.
IDT BiFIFO
Cntl A Cntl B ACK REQ CLK
Data A Data B
Control Logic
Address Control Data
Control Logic
Processor A
Processor B
Control
36-bit bus
36-bit bus
36
IDT BiFIFO
Cntl A Cntl B ACK REQ CLK 18
Data 36
RAM
RAM
Data A Data B 18
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Figure 1. 36-Bit Processor to 36-Bit Processor Configuration NOTE: 1. 36- to 36-bit processor interface configuration. Upper BiFIFO only is used in 18- to 18-bit configuration. Note that Cntl A refers to CSA, A1, A0, R/WA, and DSA; Cntl B refers to R/WB and DSB or RB and WB.
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Peripheral Interface Mode If Port B is connected to a peripheral controller, all BiFIFOs in the configuration must be programmed in peripheral interface mode. In this mode, all the Port B interface pins are all outputs. To assure fixed high states for RB and WB before they are programmed into an output, these two pins should be pulled up to VCC with 10K resistors. Of course, only one set of Port B interface pins should be used to control a single peripheral device, while the other interface pins are all ignored. Figure 2 shows a BiFIFO configuration connected to a peripheral. Port A Interface The BiFIFO is straightforward to use in microprocessorbased systems because each BiFIFO port has a standard microprocessor control set. Port A has access to six resources: the AB FIFO, the BA FIFO, the 9-bit direct data bus (bypass path), the configuration registers, status and command registers. The Port A Address and Read/Write pins determine the resource being accessed as shown in Table 1. Data Strobe is used to move data in and out of the BiFIFO.
When either of the internal FIFOs are accessed, 18 bits of data are transferred across Port A. Since the bypass path is only 9 bits wide, the least significant byte (DA0-DA7, DA16) is used on Port A. All of the registers are 16 bits wide which means only the data bits (DA0-DA15) are passed by Port A. Bypass Path The bypass path acts as a bidirectional bus transceiver directly between Port A and Port B. The direct connection requires that the Port A interface pins are inputs and the Port B interface pins are outputs. The bypass path is 9 bits wide in an 18- to 18-bit configuration or 18 bits wide in a 36- to 36bit configuration. During bypass operations, the BiFIFOs must be programmed into peripheral interface mode. Bit 10 of Configuration Register 5 (see Table 10) is set to 1 for peripheral interface mode. Command Register Ten registers are accessible through Port A, a Command Register, a Status Register, and eight Configuration Registers.
IDT BiFIFO
Cntl A Cntl B ACK REQ CLK Data A Data B DMA or System Clock
Address Control
Control Logic
Processor
Peripheral Controller
Cntl ACK REQ
36-bit bus 36-bit bus
Data 36
Data 36
IDT BiFIFO
Cntl A Cntl B ACK REQ CLK 18
I/O Data
RAM
Data A Data B 18
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Figure 2. 36-Bit Processor to 36-Bit Peripheral Configuration NOTE: 1. 36- to 36-bit peripheral interface configuration. Upper BiFIFO only is used in 18- to 18-bit configuration. Note that Cntl A refers to WA, and DSA; Cntl B refers to R/WB and DSB or RB and WB.
CSA, A1, A0, R/
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The Command Register is written by setting CSA = 0, A1 = 1, A0 = 1. Commands written into the BiFIFO have a 4-bit opcode (bit8 - bit 11) and a 3-bit operand (bit 0 - bit 2) as shown in Figure 3. The commands can be used to reset the BiFIFO, to select the Configuration Register, to perform intelligent reread/rewrite, to set the Port B DMA direction, to set the Status Register format, and to modify the Port B Read and Write Pointers. The command opcodes are shown in Table 2. The reset command initializes different portions of the BiFIFO depending on the command operand. Table 3 shows the reset command operands. The configuration Register address is set directly by the
command operands shown in Table 4. Intelligent reread/rewrite is performed by interchanging the Port B Read Pointer with the Reread Pointer or by interchanging the Port B Write Pointer with the Rewrite Pointer. No command operands are required to perform a reread/ rewrite operation. When Port B of the BiFIFO is in peripheral mode, the DMA direction is controlled by the Command Register. Table 5 shows the Port B read/write DMA direction operands. Two commands are provided to increment the Port B Read and Write Pointers. No operands are required for these commands.
COMMAND FORMAT
15 X X X 12 X 11 Command Opcode 8 7 X X X X 3 X 2 Command Operand
2668 tbl 02
0
Figure 3. Format for Commands Written into Port A
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Reset The IDT72511 and IDT72521 have a hardware reset pin (RS) that resets all BiFIFO functions. A hardware reset requires the following four conditions: RB and WB must be HIGH, RER and REW must be HIGH, LDRER and LDREW must be LOW, and DSA must be HIGH (Figure 9). After a hardware reset, the BiFIFO is in the following state: Configuration Registers 0-3 are 0000H, Configuration Register 4 is set to 6420H, and Configuration Registers 5, 6 and 7 are 0000H. Additionally, all the pointers including the Reread and Rewrite Pointers are set to 0, the DMA direction is set to BA write, and the internal DMA request circuitry is cleared (set to its initial state). A software reset command can reset AB pointers and the BA pointers to 0 independently or together. The internal
request DMA circuitry can also be reset independently. A software Reset All command resets all the pointers, the DMA request circuitry, and sets all the Configuration Registers to their default condition. Note that a hardware reset is NOT the same as a software Reset All command. Table 6 shows the BiFIFO state after the different hardware and software resets Status Register The Status Register reports the state of the programmable flags and the DMA read/write direction. The Status Register is read by setting CSA = 0, A1 = 1, A0 = 1 (see Table 1). See Table 7 for the Status Register format. Configuration Registers The eight Configuration Register formats are shown in
PORT A RESOURCE SELECTION CS A1 A0 Read CSA
0 0 0 0 1 0 0 1 1 X 0 1 0 1 X BA FIFO 9-bit Bypass Path Configuration Registers Status Register Disabled
RESET COMMAND FUNCTIONS
Write
Reset Operands 000 001 010 011
2668 tbl 03
AB FIFO 9-bit Bypass Path Configuration Registers Command Register Disabled
Function No Operation Reset BA FIFO (Read, Write, and Rewrite Pointers = 0) Reset AB FIFO (Read, Write, and Reread Pointers = 0) Reset BA and AB FIFO Reset Internal DMA Request Circuitry No Operation No Operation Reset All
2668 tbl 04
100 101 110 111
Table 1. Accessing Port A Resources Using CSA, A0 and A1
COMMAND OPERATIONS
Command Opcode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Function Reset BiFIFO (see Table 3) Select Configuration Register (see Table 4) Load Reread Pointer with Read Pointer Value Load Rewrite Pointer with Write Pointer Value Load Read Pointer with Reread Pointer Value Load Write Pointer with Rewrite Pointer Value Set DMA Transfer Direction (see Table 5) Reserved Increment AB FIFO Read Pointer (Port B) Increment BA FIFO Write Pointer (Port B) Reserved Reserved
2668 tbl 05
Table 3. Reset Command Functions
SELECT CONFIGURATION REGISTER/ COMMAND FUNCTIONS
Operands 000 001 010 011 100 101 110 111 Function Select Configuration Register 0 Select Configuration Register 1 Select Configuration Register 2 Select Configuration Register 3 Select Configuration Register 4 Select Configuration Register 5 Select Configuration Register 6 Select Configuration Register 7
2668 tbl 06
Table 4. Select Configuration Register Functions.
Table 2. Functions Performed by Port A Commands
DMA DIRECTION COMMAND FUNCTIONS
Operands XX0 XX1 Write BA FIFO Read AB FIFO
2668 tbl 07
Function
Table 5. Set DMA Direction Command Functions. Command Only Operates in Peripheral Interface Mode 5.32 8
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STATE AFTER RESET
Software Reset Hardware Reset (RS asserted) Configuration Registers 0-3 Configuration Register 4 Configuration Register 5 Configuration Register 6-7 Status Register format BA Read, Write, Rewrite Pointers AB Read, Write, Reread Pointers DMA direction DMA internal request 0000H 6420H 0000H 0000H 0 0 0 BA write clear BA and AB(011) -- -- -- -- -- 0 0 -- -- Internal Request (100) -- -- -- -- -- -- -- -- clear
BA(001) -- -- -- -- -- 0 -- -- --
AB(010) -- -- -- -- -- -- 0 -- --
All(111) 0000H 6420H 0000H 0000H -- 0 0 -- clear
2668 tbl 08
Table 6. The BiFIFO State After a Reset Command
Table 8. Configuration Registers 0-3 contain the programmable flag offsets for the Almost-Empty and Almost-Full flags. These offsets are set to 0 when a hardware reset or a software Reset All is applied. Note that Table 8 shows that Configuration Registers 0-3 are 10 bits wide to accommodate the 1024 locations in each FIFO memory of the IDT7252/520. Only 9 least significant bits are used for the 512 locations of the IDT7251/510; the most significant bit, bit 9, must be set to 0. Configuration Register 4 is used to assign the internal flags to the external flag pins (FLGA-FLGD). Each external flag pin is assigned an internal flag based on the four bit codes shown in Table 9. The default condition for Configuration Register 4 is 6420H as shown in Table 6. The default flag assignments are: FLGD is assigned BA Full, FLGC is assigned BA Empty, FLGB is assigned AB Full, FLGA is assigned AB Configuration Register 5 is a general control register. The format of Configuration Register 5 is shown in Table 10. Bit 0 sets the Intel-style interface (RB, WB) or Motorola-style interface (DSB, R/WB) for Port B. Bits 2 and 3 redefine Full and Empty Flags for reread/rewrite data protection. Bits 4-9 control the DMA interface and are only applicable in peripheral interface mode. In processor interface mode, these bits are don't care states. Bits 4 and 5 set the polarity of the DMA control pins REQ and ACK respectively. An internal clock controls all DMA operations. This internal clock is derived from the external clock (CLK). Bit 9 determines the internal clock frequency: the internal clock = CLK or the internal clock = CLK divided by 2. Bit 8 sets whether RB, WB, and DSB are asserted for either one or two internal clocks. Bits 6 and 7 set the number of internal clocks between REQ assertion and ACK assertion. The timing can be from 2 to 5 cycles as shown in Figure 17. Bit 10 controls Port B processor or peripheral interface mode. In processor mode, the Port B control pins (RB, WB, DSB, R/WB) are inputs and the DMA controls are ignored. In peripheral mode, the Port B control pins are outputs and the DMA controls are active.
Six PIO pins can be programmed as an input or output by the corresponding mask bits in Configuration Register 7. The format of Configuration Register 7 is shown in Figure 5. Each bit of the register set the I/O direction independently. A logic 1 indicates that the corresponding PIO pin is an output, while a logic 0 indicates that the PIO pin is an input. This I/O mask register can be read or written. A programmed output PIOi pin (i = 0, 1, . . . 5) displays the data latched in Bit i of Configuration Register 6. A programmed input PIOi pin allows Port A bus to sample the data on DAi by reading Configuration Register 6.
STATUS REGISTER FORMAT
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reserved Reserved Reserved DMA Direction AB Empty Flag AB Almost-Empty Flag BA Full Flag BA Almost-Full Flag Reserved Reserved Reserved Reserved AB Full Flag AB Almost-Full Flag BA Empty Flag BA Almost-Empty Flag
2668 tbl 09
Empty.
Signal
Table 7. The Status Register Format
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CONFIGURATION REGISTER FORMATS
15 10 9 0
Config. Reg. 0
X
15
X
X
X
X
X
10 9
AB FIFO Almost Empty Flag Offset
0
Config. Reg. 1
X
15
X
X
X
X
X
10 9
AB FIFO Almost Full Flag Offset
0
Config. Reg. 2
X
15
X
X
X
X
X
10 9
BA FIFO Almost Empty Flag Offset
0
Config. Reg. 3
X
15
X
X
X
12
X
11
X
8
BA FIFO Almost Full Flag Offset
7 4 3 0
Config. Reg. 4
Flag D Pin Assignment
15
Flag C Pin Assignment
Flag B Pin Assignment
Flag A Pin Assignment
0
Config. Reg. 5
15
General Control
0
Config. Reg. 6
15
I/O Data
0
Config. Reg. 7
NOTE: 1. Bit 9 of Configuration Registers 0-3 must be set to 0 on the IDT72511.
I/O Direction Control
2668 drw 02 2668 tbl 10
Table 8. The BiFIFO Configuration Register Formats
EXTERNAL FLAG ASSIGNMENT CODES
Programmable Flags The IDT BiFIFO has eight internal flags. Associated with each FIFO memory array are four internal flags, Empty, Almost-Empty, Almost-Full and Full, for the total of eight internal flags. The Almost-Empty and Almost-Full offsets can be set to any depth through the Configuration Registers 0-3 (see Table 8). The flags are asserted at the depths shown in Table 11. After a hardware reset or a software Reset All, the almost flag offsets are set to 0. Even though the offsets are equivalent, the Empty and Almost-Empty flags have different timing which means that the flags are not coincident. Similarly, the Full and Almost-Full flags are not coincident after reset because of timing. These eight internal flags can be assigned to any of four external flag pins (FLGA-FLGD) through Configuration Register 4 (see Table 9). For the specific flag timings, see Figures 20-23. The current state of all eight flags is available in the Status Register.
Assignment Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Internal Flag Assigned to Flag Pin AB Empty AB Full AB Almost-Empty AB Almost-Full BA Empty BA Full BA Almost-Empty BA Almost-Full AB Empty AB Almost-Empty AB Full AB Almost-Full BA Empty BA Almost-Empty BA Full BA Almost-Full
2668 tbl 11
Table 9. Configuration Register 4 Internal Flag Assignments to External Flag Pins
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CONFIGURATION REGISTER 5 FORMAT
Bit 0 1 2 3 4 5 7-6 Function Select Port B Interface Unused Full Flag Definition Empty Flag Definition REQ Pin Polarity ACK Pin Polarity REQ / ACK Timing 0 1 0 1 0 1 0 1 00 01 10 11 8 9 10 11 12 13 14 15 Port B Read & Write Timing Control for Peripheral Mode Internal Clock Frequency Control Port B Interface Mode Control Unused Unused Unused Unused Unused
2668 tbl 12
RB and WB or DSB and R/WB
0 1
Pins are DSB and R/WB (Motorola-style interface)
Pins are RB and WB (Intel-style interface)
Write pointer meets read pointer Write pointer meets reread pointer Read pointer meets write pointer Read pointer meets rewrite pointer REQ pin active HIGH REQ pin active LOW ACK pin active LOW ACK pin active HIGH 2 internal clocks between REQ assertion and ACK assertion 3 internal clocks between REQ assertion and ACK assertion 4 internal clocks between REQ assertion and ACK assertion 5 internal clocks between REQ assertion and ACK assertion
0 1 0 1 0 1
RB, WB, and DSB are asserted for 1 internal clock RB, WB, and DSB are asserted for 2 internal clocks
Internal clock = CLK Internal clock = CLK divided by 2 Processor interface mode (Port B controls are inputs) Peripheral interface mode (Port B controls are outputs)
Table 10. BiFIFO Configuration Register 5 Format
CONFIGURATION REGISTER 6 FORMAT
15
Unused
6
5
PIO5
4
PIO4
3
PIO3
2
PIO2
1
PIO1
0
PIO0
2668 tbl 13
Figure 4. BiFIFO Configuration Register 6 Format for Programmable I/O Data
CONFIGURATION REGISTER 7 FORMAT
15
Unused
6
5
MIO5
4
MIO4
3
MIO3
2
MIO2
1
MIO1
0
MIO0
2668 tbl 14
Figure 5. BiFIFO Configuration Register 7 Format for Programmable I/O Direction Mask
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
Port B Interface Port B has reread/rewrite and DMA functions. Port B can be configured to interface to either Intel-style (RB, WB) or Motorola-style (DSB, R/WB) devices in Configuration Register 5 (see Table 10). Port B can also be configured to talk to a processor or a peripheral device through Configuration Register 5. In processor interface mode, the Port B interface controls are inputs. In peripheral interface mode, the Port B interface controls are outputs. After a hardware reset or a software Reset All command, Port B defaults to an Intel-style processor interface; the controls are inputs. DMA Control Interface The BiFIFO has DMA control to simplify data transfers with peripherals. For the BiFIFO DMA controls (REQ, ACK and CLK) to operate, the BiFIFO must be in peripheral interface mode (Configuration Register 5, Table 10). DMA timing is controlled by the external clock input, CLK. An internal clock is derived from this CLK signal to generate the RB, WB, DSB and R/WB output signals. The internal clock also determines the timing between REQ assertion and ACK assertion. Bit 9 of Configuration Register 5 determines whether the internal clock is the same as CLK or whether the internal clock is CLK divided by 2. Bit 8 of Configuration Register 5 set whether RB, WB and DSB are asserted for 1 or 2 internal clocks. Bits 6 and 7 of Configuration Register 5 set the number of clocks between REQ assertion and ACK assertion. The clocks between REQ assertion and ACK assertion can be 2, 3, 4 or 5. Bits 4 and 5 of Configuration Register 5 set the polarity of the REQ and ACK pins respectively. A DMA transfer command sets the Port B read/write direction (see Table 5). The timing diagram for DMA transfers is shown in Figure 17. The basic DMA transfer starts with REQ assertion. After 2 to 5 internal clocks, ACK is asserted by the BiFIFO. ACK will not be asserted if a read is attempted on an empty AB FIFO or if a write is attempted on a full BA FIFO. If the BiFIFO is in Motorola-style interface mode, R/WB is set
at the same time that ACK is asserted. One internal clock later, DSB is asserted. If the BiFIFO is in Intel-style interface mode, either RB or WB is asserted one internal clock after ACK assertion. These read/write controls stay asserted for 1 or 2 internal clocks, then ACK, DSB, RB and WB are made inactive. This completes the transfer of one 9-bit word. On the next rising edge of CLK, REQ is sampled. If REQ is still asserted, another DMA transfer starts with the assertion of ACK. Data transfers will continue as long as REQ is asserted. Intelligent Reread/Rewrite Intelligent reread/rewrite is a method the BiFIFO uses to help assure data integrity. Port B of the BiFIFO has two extra pointers, the Reread Pointer and the Rewrite Pointer.The Reread Pointer is associated with the A->B FIFO Read Pointer, while the Rewrite Pointer is associated with the B->A FIFO Write Pointer. The Reread Pointer holds the start address of a data block in the A->B FIFO RAM, and the Read Pointer is the current address of the same FIFO RAM array. By loading the Read Pointer with the value held in the Reread Pointer (RER asserted), reads will start over at the beginning of the data block. In order to mark the beginning of a data block, the Reread Pointer should be loaded with the Read Pointer value (LDRER asserted) before the first read is performed on this data block. Figure 6 shows a Reread operation. Similarly, the Rewrite Pointer holds the start address of a data block in the B->A FIFO RAM, while the Write Pointer is the current address within the RAM array. The operation of the REW and LDREW is identical to the RER and LDRER discussed above. Figure 7 shows a Rewrite operation. For the reread data protection, Bit 2 of Configuration Register 5 can be set to 1 to prevent the data block from being overwritten. In this way, the assertion of A->B full flag will occur when the write pointer meets the reread pointer instead of the read pointer as in the normal definition. For the rewrite data protection, Bit 3 of Configuration Register 5 can be set to 1 to
INTERNAL FLAG TRUTH TABLE
Number of Words in FIFO From 0 1 n+1 D-m D To 0 n D - (m + 1) D-1 D Empty Flag Asserted Not Asserted Not Asserted Not Asserted Not Asserted Almost-Empty Flag Asserted Asserted Not Asserted Not Asserted Not Asserted Almost-Full Flag Not Asserted Not Asserted Not Asserted Asserted Asserted Full Flag Not Asserted Not Asserted Not Asserted Not Asserted Asserted
NOTE: 2668 tbl 15 1. BiFIFO flags must be assigned to external flag pins to be observed. D = FIFO depth (IDT72511 = 512, IDT72521 = 1024), n = Almost-Empty flag offset, m = Almost-Full flag offset.
Table 11. Internal Flag Truth Table
5.32
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IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
prevent the data block from being read. In this case the assertion of B->A empty flag will occur when the read pointer meets the rewrite pointer instead of the write pointer. In conclusion, Bit 2 and 3 of Configuration Register 5 are used to redefine Full & Empty flags for data block partition. Although it can serve the purpose of data protection, the setting of these 2 bits is independent of the functions caused by RER/REW, or LDRER/LDREW assertions. Programmable Input/Output The BiFlFO has six programmable I/0 pins (PlO0 - PIO5) which are controlled by Port A through Configuration Registers 6 and 7. Data from the programmable I/O pins is mapped directly to the six least significant bits of Configuration Regis-
ter 6. Figure 4 shows the format of Configuration Register 6. This data is read or written by Port A on the data pins (DA0- DA5). A programmed output PIOi pin (i = 0, 1, . . . , 5) displays the data latched in Bit i of Configuration Register 6. A programmed input PIOi pin allows Port A bus to sample its data on DAi by reading Configuration Register 6. The read and write timing for the programmable I/O pins is shown in Figure 19. The direction of each programmable I/O pin can be set independently by programming the mask in Configuration Register 7. Each P10 pin has a corresponding input/output direction mask bit in Configuration Register 7. Figure 5 shows the format of Configuration Register 7. Setting a mask bit to a logic 1 makes the corresponding I/O pin an output. Mask bits set to logic 0 force the corresponding I/O pin to an input.
REREAD OPERATIONS (1,2)
Reread Pointer Reread function
REWRITE OPERATIONS (3,4)
Read Pointer
Write Pointer
AB FIFO
Load Reread function
Write Pointer
BA FIFO
Load Rewrite function Rewrite Pointer
Read Pointer
2668 drw 08
Rewrite function
NOTES: 1. If bit 3 is set to 1, Empty flag asserted if Read = Rewrite Full flag asserted if Read + FIFO size = Write 2. If bit 3 is set to 0, Empty flag asserted if Read = Write Full flag asserted if Read + FIFO size = Write Figure 7. BiFIFO Rewrite Operations
NOTES: 1. If bit 2 is set to 1, Empty flag asserted if Read = Write Full flag asserted if Reread + FIFO size = Write 2. If bit 2 is set to 0, Empty flag asserted if Read = Write Full flag asserted if Read + FIFO size = Write Figure 6. BiFIFO Reread Operations
2668 drw 09
5.32
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IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage With Respect To Ground Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial -0.5 to +7.0 Military -0.5 to +7.0 Unit V
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCCM Parameter Military Supply Voltage Commercial Supply Voltage Supply Voltage Input HIGH Voltage Commercial Input HIGH Voltage Military Input LOW Voltage Commercial and Military Min. 4.5 4.5 0 2.0 2.2 -- Typ. 5.0 5.0 0 -- -- -- Max. 5.5 5.5 0 -- -- 0.8 Unit V V V V V V
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -55 to +125 50
-55 to +125 -65 to +135 -65 to +155 50
C C C
mA
VCCC GND VIH VIH VIL(1)
NOTE: 2668 tbl 16 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle.
2668 tbl 17
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to +70C; Military: VCC = 5V 10%, TA = -55C to +125C)
IDT72511L IDT72521L Commercial tA = 25, 35, 50ns Min. Typ. Max. -1 -10 2.4 -- -- -- -- -- -- -- 150 16 1 10 -- 0.4 230 30 IDT72521L Military tA = 40, 50ns Typ. -- -- -- -- 180 24
Symbol I
IL (1)
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage I OUT = -1mA Output Logic "0" Voltage IOUT = 4mA Average VCC Power Supply Current Average Standby Current (RB = WB = DSA = VIH)
Min. -10 -10 2.4 -- -- --
Max. 10 10 -- 0.4 250 50
Unit
A A
V V mA mA
2668 tbl 18
IOL(2) VOH VOL ICC1 (3)(4) ICC2 (3)
NOTES: 1. Measurements with 0.4V VIN VCC, DSA = DSB VIH 2. Measurements with 0.4V VOUT VCC, DSA = DSB VIH 3. Measurements are made with outputs open.
+5V
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 8
2668 tbl 19
1.1 k D.U.T. 680 30 pF*
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN (2) COUT (1,2) Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 12 Unit pF pF
2668 tbl 20
2668 drw 09
or equivalent circuit
Figure 8. Output Load *Includes jig and scope capacitances
NOTES: 1. With output deselected. 2. Characterized values, not currently tested.
5.32
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IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to + 70C; Military: VCC = 5V 10%, TA = -55C to + 125C)
Commercial IDT72511L25 IDT72521L25 Symbol tRSC tRS tRSS tRSR tRSF taA taLZ Parameter Reset cycle time Reset pulse width Reset set-up time Reset recovery time Reset to flag time Port A access time Read or write pulse LOW to data bus at Low-Z Read or write pulse HIGH to data bus at High- Z Data valid from read pulse HIGH Read cycle time Read pulse width Read recovery time Min. 35 25 25 10 -- -- 5 Max. -- -- -- -- 35 25 -- RESET TIMING (Port A and Port B) 45 35 35 10 -- -- 5 -- -- -- -- 45 35 -- 50 40 40 10 -- -- 5 -- -- -- -- 50 40 -- 65 50 50 15 -- -- 5 -- -- -- -- 65 50 -- ns ns ns ns ns ns ns 9 9 9 9 9 12, 14, 15 12, 15, 16 IDT72511L35 IDT72521L35 Min. Max. IDT72521L40 Min. Max. Military Com'l & Mil.(2) IDT72511L50 IDT72521L50 Min. Max. Unit Timing Figure
PORT A TIMING
taHZ
--
15
--
20
--
25
--
30
ns
12, 14, 15, 16
taDV taRC taRPW taRR taS taH taDS taDH(1) taWC taWPW taWR taWRCOM
5 35 25 10 5 5 15 0 35 25 10 25
-- -- -- -- -- -- -- -- -- -- -- --
5 45 35 10 5 5 18 2 45 35 10 35
-- -- -- -- -- -- -- -- -- -- -- --
5 50 40 10 5 5 20 5 50 40 10 40
-- -- -- -- -- -- -- -- -- -- -- --
5 65 50 15 5 5 30 5 65 50 15 50
-- -- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns
12, 14, 16 12 12, 14, 15 12 10, 12, 16 10, 12 11, 12, 14, 15 11, 12, 14, 15 12 11, 12, 14 12 11
2668 tbl 21
CSA, A0, A1, R/WA set up time time
CSA, A0, A1, R/WA hold
Data set-up time Data hold time Write cycle time Write pulse width Write recovery time Write recovery time after a command
NOTE: 1. The minimum data hold time is 5ns (10ns for the 80ns speed grade) when writing to the Command or Configuration registers. 2. IDT72511 not available in military.
5.32
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IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to + 70C; Military: VCC = 5V 10%, TA = -55C to + 125C)
Commercial IDT72511L25 IDT72521L25 Symbol Parameter Min. Max. PORT B PROCESSOR INTERFACE TIMING tbA tbLZ Port B access time Read or write pulse LOW to data bus at Low-Z Read or write pulse HIGH to data bus at High-Z Data valid from read pulse HIGH Read cycle time Read pulse width Read recovery time R/WB set-up time R/WB hold time Data set-up time Data hold time Write cycle time Write pulse width Write recovery time -- 5 25 -- -- 5 35 -- -- 5 40 -- -- 5 50 -- ns ns 13, 14, 15 13, 14, 15 IDT72511L35 IDT72521L35 Min. Max. IDT72521L40 Min. Max. Military Com'l & Mil.(1) IDT72511L50 IDT72521L50 Min. Max. Unit Timing Figure
tbHZ
--
15
--
20
--
25
--
30
ns
14, 13, 15
tbDV tbRC tbRPW tbRR tbS tbH tbDS tbDH tbWC tbWPW tbWR
5 35 25 10 5 5 15 0 35 25 10
-- -- -- -- -- -- -- -- -- -- --
5 45 35 10 5 5 18 2 45 35 10
-- -- -- -- -- -- -- -- -- -- --
5 50 40 10 5 5 20 5 50 40 10
-- -- -- -- -- -- -- -- -- -- --
5 65 50 15 5 5 30 5 65 50 15
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns
13, 14, 15, 16 13 13 13 13 13 13, 14, 15 13, 14, 15 13 13, 15 13
PORT B PERIPHERAL INTERFACE TIMING tbA tbCKC tbCKH tbCKL tbREQS tbREQH tbACKL Port B access time Clock cycle time Clock pulse HIGH time Clock pulse LOW time Request set-up time Request hold time Delay from a rising clock edge to ACK switching -- 15 6 6 5 5 -- 25 -- -- -- -- -- 15 -- 20 6 6 5 5 -- 40 -- -- -- -- -- 18 -- 20 8 8 5 5 -- 45 -- -- -- -- -- 20 -- 25 10 10 10 5 -- 55 -- -- -- -- -- 25 ns ns ns ns ns ns ns 17 17 17 17 17 17 17
NOTE: 1. IDT72511 not available in military.
2668 tbl 22
5.32
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IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to + 70C; Military: VCC = 5V 10%, TA = -55C to + 125C)
Commercial IDT72511L25 IDT72521L25 Symbol Parameter Min. Max. PORT B RETRANSMIT TIMING tbDSBH IDT72511L35 IDT72521L35 Min. Max. IDT72521L40 Min. Max. Military Com'l & Mil.(4) IDT72511L50 IDT72521L50 Min. Max. Unit Timing Figure
RER, REW, LDRER,
LDREW set-up and recovery time
10
--
10
--
10
--
15
--
ns
9, 18
PROGRAMMABLE I/O TIMING tPIOA tPIOS tPIOH Programmable I/O access time Programmable I/O setup time Programmable I/O hold time Bypass access time Bypass delay Bypass data valid time from DSA -- 8 8 20 -- -- -- 10 10 25 -- -- -- 10 10 25 -- -- -- 15 15 30 -- -- ns ns ns 19 19 19
BYPASS TIMING tBYA tBYD taBYDV -- -- 15 3 18 10 -- -- -- -- 15 3 20 15 -- -- -- -- 15 3 25 20 -- -- -- -- 15 3 30 20 -- -- ns ns ns ns 16 16 16 16
tbBYDV (3) Bypass data valid time from DSB FLAG TIMING (1) (2) tREF tWEF tRFF tWFF tRAEF Read clock edge to Empty Flag asserted Write clock edge to Empty Flag not asserted Read clock edge to Full Flag not asserted Write clock edge to Full Flag asserted Read clock edge to Almost-Empty Flag asserted Write clock edge to Almost-Empty Flag not asserted Read clock edge to Almost-Full Flag not asserted Write clock edge to Almost-Full Flag asserted
-- -- -- -- --
25 25 25 25 40
-- -- -- -- --
35 35 35 35 50
-- -- -- -- --
40 40 40 40 55
-- -- -- -- --
45 45 45 45 60
ns ns ns ns ns
14, 15, 20, 22 14, 15, 20, 22 14, 15, 21, 23 14, 15, 21, 23 20, 22
tWAEF
--
40
--
50
--
55
--
60
ns
20, 22
tRAFF
--
40
--
50
--
55
--
60
ns
21, 23
tWAFF
--
40
--
50
--
55
--
60
ns
21, 23
NOTES: 2668 tbl 23 1. Read and write are internal signals derived from DSA, R/WA, DSB, R/WB, RB, and WB. 2. Although the flags, Empty, Almost-Empty, Almost-Full, and Full Flags are internal flags, the timing given is for those assigned to external pins. 3. Values guaranteed by design, not currently tested. 4. IDT72511 not available in military.
5.32
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IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tRSC tRS
RS
tRSS (or R/WB, DSB)
tRSR
WB, RB RER, REW
LDRER, LDREW REQ tRSR
DSA
tRSF FLGA, FLGC tRSF FLGB, FLGD
2668 drw 10
Figure 9. Hardware Reset Timing
CSA
A0, A1
R/WA
DSA
taS taH
2668 drw 11
Figure 10. Basic Port A Control Signal Timing (Applies to All Port A Timing)
5.32
18
IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
R/WA
tWPW
DSA
tWRCOM Opcode DA8 - DA12 or Operand DA0 - DA12
2668 drw 12
taDS
taDH
Figure 11. Port A Command Timing (write).
WRITE
R/WA taWC
taWPW
DSA
taS taRR taH
Input DA0 - DA17 taDS taDH
READ
R/WA taRC taRPW
DSA
taS taRR taH Output DA0 - DA17 taLZ taA taDV taHZ
2668 drw 13
Figure 12. Read and Write Timing for Port A
5.32
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IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WRITE
tbWC
(R/WB)
(or DSB) tbS
WB
tbWPW
tbWR tbH
Input DB0-DB8 tbDS
NOTE: 1.
tbDH
RB = 1
READ
(R/WB) (or DSB) tbRPW tbS Output DB0-DB8 tbLZ tbA
tbRC
RB
tbRR tbH
tbDV tbHZ
2668 drw 14
NOTE: 1.
WB = 1
Figure 13. Port B Read and Write Timing, Processor Interface Mode Only
5.32
20
IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AB FIFO WRITE FLOW-THROUGH
taWPW
DSA
DA0 - DA17 DATA INPUTS taDS AB (1) Full Flag taDH
RB (or DSB)
tbLZ DB0 - DB17 DATA OUT tbA
NOTES: 1. Assume the flag pin is programmed active LOW. 2. R/WA = 0
tRFF
tWFF
tbDV
tbHZ
BA FIFO READ FLOW-THROUGH
taRPW
DSA
taLZ DA0 - DA17 taA taDV DATA OUTPUT taHZ BA Empty Flag (1) tWEF tREF
WB (or DSB)
DB0 - DB17 DATA INPUT tbDS tbDH
2668 drw 15
NOTES: 1. Assume the flag pin is programmed active LOW. 2. R/WA = 1
Figure 14. Port A Read and Write Flow-Through Timing, Processor Interface Mode Only
5.32
21
IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AB FIFO WRITE FLOW-THROUGH
DSA
taLZ DA0-DA17 tbA BA Full Flag(1)DATA OUT taHZ
RB = 1 (or R/WB = 0) WB (or DSB)
DB0-DB8
NOTES: 1. Assume the flag pin is programmed active LOW. 2. R/WA = 1
tRFF
tWFF
tbWPW DATA INPUT tbDS tbDH
AB FIFO READ FLOW-THROUGH
DSA
DA0-DA17 taDS AB Empty Flag (1)
DATA INPUT taDH
tWEF
WB = 1 (or R/WB = 1) RB (or DSB)
taLZ DB0-DB8 tbA
NOTES: 1. Assume the flag pin is programmed active LOW. 2. R/WA = 0
tREF
DATA OUT tbDV taHZ
2668 drw 16
tbRPW
Figure 15. Port B Read and Write Flow-Through Timing, Processor Interface Mode Only
5.32
22
IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BA READ BYPASS
R/WA
taS
taH
DSA
taLZ DA0-DA7, DA16 tBYA BYTE 0 (1) taDV BYTE 1 taHZ BYTE 2
RB (or DSB)
tBYD tBYD
(R/WB) tBYD (1) DB0-DB8
NOTES: 1. Once the bypass mode starts, any data change on Port B bus (Byte 0Byte 1) will be passed to Port A bus. 2. WB = 1
tBYD BYTE 1
tBYD BYTE 2
BYTE 0
AB WRITE BYPASS
R/WA taS taH
DSA
tBYD (1) DA0-DA7, DA16 BYTE 0 BYTE 1 BYTE 2
tBYD
WB (or DSB)
tBYD (R/WB) tbLZ DB0-DB8 tBYA (1) BYTE 0 BYTE 1 tbHZ
2668 drw 17
tBYD tbBYDV taBYDV BYTE 2
tBYD
NOTES: 1. Once the bypass mode starts, any data change on Port A bus (Byte 0Byte 1) will be passed to Port B bus. 2. RB = 1 Figure 16. Bypass Path Timing, BiFIFO Must Be in Peripheral Interface Mode
5.32
23
IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SINGLE WORD DMA TRANSFER
2 to 5 cycles tCKC tCKH CLK REQ tREQS tREQH tCKL 1 cycle 1 to 2 cycles
ACK
WRITE
(R/WB)
WB (or DSB)
Output DB0-DB17
tACKL
taCKL
taCKL
tbLZ
tbDV tbHZ
READ
(R/WB)
tbA
RB (or DSB)
tACKL Input DB0-DB17 tbDS tbDH tACKL
BLOCK DMA TRANSFER
2 to 5 cycles CLK REQ 1 to 2 cycles 2 to 5 cycles 1 to 2 cycles
ACK, R/WB RB, WB (or DSB)
2668 drw 18
Figure 17. Port B Read and Write DMA timing. Peripheral Interface Mode Only
5.32
24
IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(or R/WB, DSB)
RB, WB RER REW
tbDSBH
tbWPW
tbDSBH
LDRER, LDREW
2668 drw 19
Figure 18. Port B Reread and Rewrite Timing for Intelligent Reread/Rewrite
Port A PIO WRITE
taWC R/WA
DSA
taWPW taS
taWR taH
Input DA0-DA5 taDS Output PIO0-PIO5 tPIOA tPIOH taDH
PIO Port A READ
R/WA taRC
DSA
taS Output DA0-DA5 taLZ
taRPW
taRR
taH
taDV taA taHZ
Input PIO0-PIO5 tPIOS tPIOH
2668 drw 20
Figure 19. Programmable I/O Timing
5.32
25
IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DSA
(or R/WB = 0, DSB)
Read 1 2 n+1
WB
Write 1 2 tWEF n+1 tREF
BA Empty Flag tWAEF BA AlmostEmpty Flag
2668 drw 21
tRAEF
NOTES: 1. BA FIFO is initially empty. 2. Assume the flag pins are programmed active LOW. 3. R/WA = 1. Figure 20. Empty and Almost-Empty Flag Timing for BA FIFO, (n = programmed offset)
DSA WB
Write 1 2 tWEF
(2)
Read 1 2 m+1
(or R/WB=1, )
m+1 tRAFF
BA AlmostFull Flag
(2)
tWFF
tRFF
BA Full Flag
2668 drw 22
NOTES: 1. BA FIFO initially contains D - (M + 1) data words. D = 512 for IDT72511; D = 1024 for IDT72521. 2. Assume the flag pins are programmed active LOW. 3. R/WA = 1.
Figure 21. Full and Almost-Full Flag Timing for BA FIFO, (m = programmed offset)
5.32
26
IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Write DSA 1 (or R/WB=1, DSB) tWEF AB Empty (2) Flag tWAE
F
2
n+1 Read 1 2 tREF n+1
RB
tRAEF
AB Almost- (2) Empty Flag
2668 drw 23
NOTES: 1. AB FIFO is initially empty. 2. Assume the flag pins are programmed active LOW. 3. R/WA = 1. Figure 22. Empty and Almost-Empty Flag Timing for AB FIFO, (n = programmed offset)
Read
DSA
(or R/WB=1, DSB)
1 Write 1 2 tWEF m+1
2
m+1
WB
(2)
tRAFF
BA AlmostFull Flag
(2)
tWFF
tRFF
BA Full Flag
2668 drw 24
NOTES: 1. BA FIFO initially contains D - (M + 1) data words. D = 512 for IDT72511; D = 1024 for IDT72521. 2. Assume the flag pins are programmed active LOW. 3. R/WA = 1. Figure 23. Full and Almost-Full Flag Timing for AB FIFO, (m = programmed offset)
5.32
27
IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type X Power XXX Speed X Package X Process/ Temperature Range Blank B Commercial (0C to +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B 68-pin PGA 68-pin PLCC Commercial Only Commercial Only Military Only * Com'l & Mil. *
G J 25 35 40 50
Access Time (tA ) in ns
L 72511 72521
Low Power 512 x 18 Parallel BiFIFO 1024 x 18 Parallel BiFIFO
2668 drw 25
* 40 Military Only, IDT72521 * 50 Commercial and Military, IDT72511 available in commercial only
5.32
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